The growing demands of mobile computing and data centers continue to drive the need for high-capacity, high-performance NAND flash technology. With planar NAND nearing its practical scaling limits, NAND flash memory has moved from a planar configuration to a vertical configuration (VNAND). This vertical configuration permits the memory devices to be formed at significantly greater bit density. In manufacturing stacking of 3D semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
When forming features, such as trenches or vias, in stair-like structures in a film stack disposed on a substrate, an etch process using a photoresist layer as an etching mask is often utilized. The film stack typically includes multiple material layers in which the features, such as trenches or contact holes, are formed with high aspect ratios. High aspect ratio is generally defined as the ratio between the depth of the feature and the width of the feature, for at least about 20:1 and greater. In an exemplary embodiment depicted in FIG. 4 (Prior Art), a photoresist layer (not shown) may serve as an etching mask layer to transfer structures onto a film stack 400 disposed on a substrate 404 to form stair-like structures 410 on the substrate 404. The film stack 300 typically includes alternating layers of layers 402a, 402b (shown as 402a1, 402b1, 402a2, 402b2, . . . , 402n1, 402n2), either conductive layers or insulating layers. For example, the film stack may include alternating layers of SiO2/Si, SiO/SiN, SiO2/W, or W/TiN with thickness up to several microns. One of these two materials needs to be etched or recessed selectively within the contact holes to form memory cells.
During etching, features 430 with high aspect ratio, such as greater than about 5:1 or above, for example about 10:1 or above, may be formed into the film stack 400. Due to the high aspect ratio, however, it has been challenging for traditional plasma dry etch or wet etch to etch the sidewall W/TiN Si, or SiN uniformly from the top portion of the contact holes to the bottom portion of the contact holes, causing greater recessing of the material, for example tungsten, near the top portion of the contact holes than at the bottom portion (i.e., irregular dimensional profiles of the etched structures). In addition, redeposition or build-up of by-products or other materials generated during the etch process may accumulate and/or attach on the top and/or sidewalls of the features 430, 432, 434 being etched, thereby blocking the opening the feature 430, 432, 434 being formed in the film stack 400 and thus preventing etching through the entire film stack 400. Moreover, as the opening of the etched features 432 are narrowed and/or sealed by the accumulated redeposition material, the reactive etchants are prevented from reaching the lower surface 433 of the features 432, thereby limiting the aspect ratio that may be obtained.
Thus, there is a need for improved methods for forming high aspect ratio features, such as forming features in stair-like structures, with accurate profiles and dimension control for three dimensional (3D) stacking of semiconductor chips.